Very-large-scale integration (“VLSI”) circuits and other integrated circuits are made up of interconnected cells that include a group of transistors and interconnect structures. Each cell must be powered from a power supply through a power grid. The power grid of the circuit refers to the wires or buses used to supply current to the logic devices of each cell and to ground buses used to take current away.
As electronic circuit densities increase and technology advances, for example, in deep-sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and the manufacturability and reliability of the circuit. One area where design layout is particularly important is in the area of metal layers and vias. A via is used to connect, for example, two design geometries, one on each of two consecutive conductive layers (e.g., a metal line on each of two consecutive metal layers) of an electronic circuit. For example, it can be important to ensure that each connection area between two conductive layers has at least a certain number of vias and/or has vias placed appropriately to reduce the risk of via failure due to vacancy concentration of isolated vias.
However, correctly placing vias in an IC design is a very complex process. An electronic design automation (“EDA”) tool or any computer based circuit design tool generally requires a long time to determine via placement for a dense circuit, and generates a very large database. For example, the fastest EDA tools typically require approximately 4 hours to generate a large via database on a 1500×3000 micron integrated circuit design.